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 EMC1428 1C Multiple Temperature Sensor with HW Thermal Shutdown & Hottest of Thermal Zones
PRODUCT FEATURES
General Description
The EMC1428 is a high accuracy, low cost, System Management Bus (SMBus) temperature sensor. Advanced features such as Resistance Error Correction (REC), Beta Compensation (to CPU diodes requiring the BJT or transistor model) and automatic diode type detection combine to provide a robust solution for complex environmental monitoring applications. Additionally, the EMC1428 provides a hardware programmable system shutdown feature that is programmed at part power-up via a single TRIP_SET voltage channel that cannot be masked or corrupted through the SMBus. Each device provides 1 accuracy for external diode temperatures and 2C accuracy for the internal diode temperature. The EMC1428 monitors up to eight temperature channels (up to seven external and one internal). Datasheet
Features
Hardware Thermal Shutdown
-- triggers dedicated SYS_SHDN pin -- hardware configured range 65C to 127C in 1C steps -- cannot be disabled or modified by software
Designed to support 45nm, 65nm, and 90nm CPU diodes Supports diodes requiring the BJT or transistor model Resistance Error Correction (up to 100 Ohms) Up to seven External Temperature Monitors
-- -- -- -- 1C Accuracy (60C < TDIODE < 100C) 0.125C Resolution Supports up to 2.2nF filter capacitor Anti-parallel diodes for extra diode support and compact design
Internal Temperature Monitor
-- 2C accuracy
Applications
Notebook Computers Desktop Computers Industrial Embedded Applications
3.3V Supply Voltage Available in a 16 pin 4mm x 4mm QFN lead-free RoHS Compliant package Programmable temperature limits for ALERT
Block Diagram
TRIP_SET SYS_SHDN
DP1 DN1 DP2 / DN3 DN2 / DP3 DP4 / DN5 DN4 / DP5 DP6 / DN7 DN6 / DP7
Critical / Thermal Shutdown Logic External Temp Diode Inputs Analog Mux
Voltage to Temp conversion Voltage Register
SMCLK SMDATA SMBus Slave Protocol ALERT
11 bit ADC
Temp Registers
Antiparallel diode
Hottest of Comparison Internal Temp Diode
SMSC EMC1428
DATASHEET
Revision 0.62 (03-05-08)
1C Multiple Temperature Sensor with HW Thermal Shutdown & Hottest of Thermal Zones
Datasheet
ORDER NUMBERS:
ORDERING NUMBER EMC1428-1-AP PACKAGE 16 pin QFN (Lead-Free RoHS Compliant) 16 pin QFN (Lead-Free RoHS Compliant) FEATURES Up to 7 external diodes. "Hottest Of" temperature comparison. Hardware set Critical / Thermal shutdown, ALERT output Up to 7 external diodes. "Hottest Of" temperature comparison. Hardware set Critical / Thermal shutdown, ALERT output DIODE MODES SUPPORTED Intel CPU and 3904 SMBUS ADDRESS 1001_100(r/w)
EMC1428-6-AP
Intel CPU and 3904
1001_101(r/w)
80 ARKAY DRIVE, HAUPPAUGE, NY 11788 (631) 435-6000, FAX (631) 273-3123 Copyright (c) 2008 SMSC or its subsidiaries. All rights reserved. Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications. Consequently, complete information sufficient for construction purposes is not necessarily given. Although the information has been checked and is believed to be accurate, no responsibility is assumed for inaccuracies. SMSC reserves the right to make changes to specifications and product descriptions at any time without notice. Contact your local SMSC sales office to obtain the latest specifications before placing your product order. The provision of this information does not convey to the purchaser of the described semiconductor devices any licenses under any patent rights or other intellectual property rights of SMSC or others. All sales are expressly conditional on your agreement to the terms and conditions of the most recently dated version of SMSC's standard Terms of Sale Agreement dated before the date of your order (the "Terms of Sale Agreement"). The product may contain design defects or errors known as anomalies which may cause the product's functions to deviate from published specifications. Anomaly sheets are available upon request. SMSC products are not designed, intended, authorized or warranted for use in any life support or other application where product failure could cause or contribute to personal injury or severe property damage. Any and all such uses without prior written approval of an Officer of SMSC and further testing and/or modification will be fully at the risk of the customer. Copies of this document or other SMSC literature, as well as the Terms of Sale Agreement, may be obtained by visiting SMSC's website at http://www.smsc.com. SMSC is a registered trademark of Standard Microsystems Corporation ("SMSC"). Product names and company names are the trademarks of their respective holders. SMSC DISCLAIMS AND EXCLUDES ANY AND ALL WARRANTIES, INCLUDING WITHOUT LIMITATION ANY AND ALL IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND AGAINST INFRINGEMENT AND THE LIKE, AND ANY AND ALL WARRANTIES ARISING FROM ANY COURSE OF DEALING OR USAGE OF TRADE. IN NO EVENT SHALL SMSC BE LIABLE FOR ANY DIRECT, INCIDENTAL, INDIRECT, SPECIAL, PUNITIVE, OR CONSEQUENTIAL DAMAGES; OR FOR LOST DATA, PROFITS, SAVINGS OR REVENUES OF ANY KIND; REGARDLESS OF THE FORM OF ACTION, WHETHER BASED ON CONTRACT; TORT; NEGLIGENCE OF SMSC OR OTHERS; STRICT LIABILITY; BREACH OF WARRANTY; OR OTHERWISE; WHETHER OR NOT ANY REMEDY OF BUYER IS HELD TO HAVE FAILED OF ITS ESSENTIAL PURPOSE, AND WHETHER OR NOT SMSC HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
Revision 0.62 (03-05-08)
2
SMSC EMC1428
DATASHEET
1C Multiple Temperature Sensor with HW Thermal Shutdown & Hottest of Thermal Zones
Datasheet
Table of Contents
Chapter 1 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Chapter 2 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1 2.2 2.3 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 SMBus Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Chapter 3 System Management Bus Interface Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 System Management Bus Interface Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Write Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Read Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Send Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Receive Byte. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Alert Response Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SMBus Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SMBus Timeout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 12 13 13 13 13 14 14
Chapter 4 Product Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.1 ALERT Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.1 ALERT Pin Interrupt Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.2 ALERT Pin Comparator Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SYS_SHDN Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TRIP_SET Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Consecutive Alerts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Temperature Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5.1 Resistance Error Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5.2 Beta Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5.3 Digital Averaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5.4 "Hottest Of" Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5.5 Conversion Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5.6 Dynamic Averaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Diode Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.6.1 Diode Faults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 16 16 16 17 19 19 19 20 20 20 20 20 21 21
4.2 4.3 4.4 4.5
4.6
Chapter 5 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 5.10 5.11 5.12 5.13 5.14 5.15 5.16 Data Read Interlock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Temperature Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Conversion Rate Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Limit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Therm Hysteresis Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Therm Limit Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Diode Fault Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TRIP_SET Reading Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Software Thermal Shutdown Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Hardware Critical / Thermal Shutdown Limit Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Channel Interrupt Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Consecutive ALERT Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Beta Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Hottest Temperature Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3
27 27 28 29 29 30 33 33 34 35 35 36 36 37 38 39
SMSC EMC1428
Revision 0.62 (03-05-08)
DATASHEET
1C Multiple Temperature Sensor with HW Thermal Shutdown & Hottest of Thermal Zones
Datasheet
5.17 5.18 5.19 5.20 5.21 5.22 5.23 5.24 5.25 5.26 5.27
Hottest Temperature Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . High Limit Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low Limit Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . THERM Limit Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REC Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Hottest Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Channel Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Filter Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Manufacturer ID Register (FEh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Revision Register (FFh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
40 40 41 41 42 42 43 44 44 44 44
Chapter 6 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
6.1 EMC1428 Package Drawing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Revision 0.62 (03-05-08)
4
SMSC EMC1428
DATASHEET
1C Multiple Temperature Sensor with HW Thermal Shutdown & Hottest of Thermal Zones
Datasheet
List of Figures
Figure 1.1 Figure 3.1 Figure 4.1 Figure 4.2 Figure 4.3 Figure 4.4 Figure 6.1 Figure 6.2 Figure 6.3 EMC1428 Pin Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 SMBus Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 System Diagram for EMC1428 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Block Diagram of Hardware Thermal Shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Vset Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Diode Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 16 pin QFN 4mm x 4mm Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 16 pin QFN 4mm x 4mm Package Drawing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 16 pin QFN 4mm x 4mm PCB Footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
SMSC EMC1428
5
Revision 0.62 (03-05-08)
DATASHEET
1C Multiple Temperature Sensor with HW Thermal Shutdown & Hottest of Thermal Zones
Datasheet
List of Tables
Table 1.1 EMC1428 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 1.2 Pin Type. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Table 2.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Table 2.2 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Table 2.3 SMBus Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Table 3.1 Protocol Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Table 3.2 Write Byte Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Table 3.3 Read Byte Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Table 3.4 Send Byte Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Table 3.5 Receive Byte Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Table 3.6 Alert Response Address Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Table 4.1 VTRIP Resistor Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 4.2 Supply Current vs. Conversion Rate for EMC1428 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 5.1 Register Set in Hexadecimal Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Table 5.2 Temperature Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 5.3 Temperature Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 5.4 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 5.5 Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 5.6 Conversion Rate Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 5.7 Conversion Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 5.8 Maximum Conversion Rate Per Temperature Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 5.9 Temperature Limit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 5.10 Therm Hysteresis Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 5.11 Therm Limit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 5.12 External Diode Fault Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 5.13 TRIP_SET Reading Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Table 5.14 Software Thermal Shutdown Configuration Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Table 5.15 Hardware Thermal Shutdown Limit Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Table 5.16 Channel Interrupt Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Table 5.17 Consecutive ALERT Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Table 5.18 Consecutive Alert Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Table 5.19 Beta Configuration Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Table 5.20 Beta Compensation Look Up Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Table 5.21 Hottest Temperature Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Table 5.22 Hottest Temperature Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Table 5.23 High Limit Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Table 5.24 Low Limit Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Table 5.25 THERM Limit Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Table 5.26 REC Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Table 5.27 Hottest Configuration Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Table 5.28 Channel Configuration Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Table 5.29 Filter Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Table 5.30 Product ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Table 5.31 Manufacturer ID Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Table 5.32 Revision Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
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Chapter 1 Pin Description
VDD
DN6 / DP7
14
DP6 / DN7
16
15
DP1 DN1 DP2 / DN3 DN2 / DP3
1 2 3 4 5
13 12 11 10 9
N/C
EMC1428 16 QFN
SMCLK SMDATA DP4 / DN5 DN4 / DP5
6
7
SYS_SHDN
Figure 1.1 EMC1428 Pin Diagram
Table 1.1 EMC1428 Pin Description PIN NUMBER 1 2 3 NAME DP1 DN1 DP2 / DN3 FUNCTION DP1 - External Diode 1 positive (anode) connection. External Diode 1 negative (cathode) connection. External Diode 2 positive (anode) connection and External Diode 3 negative (cathode) connection External diode 2 negative (cathode) connection and External Diode 3 positive (anode) connection Voltage input to set Critical / Thermal Shutdown temperature Active low System Shutdown output signal - requires pull-up resistor. TYPE AIO AIO AIO
4
DN2 / DP3
TRIP_SET
ALERT
GND
8
AIO
5 6
TRIP_SET SYS_SHDN
AIO OD (5V)
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Table 1.1 EMC1428 Pin Description (continued) PIN NUMBER 7 8 9 NAME ALERT GND DN4 / DP5 FUNCTION Active low interrupt - requires pull-up resistor., Ground Connection External diode 4 negative (cathode) connection and External Diode 5 positive (anode) connection External Diode 4 positive (anode) connection and External Diode 5 negative (cathode) connection SMBus Data input/output SMBus Clock input Not used - connect to Ground - see EMC1428 Anomaly Sheet External diode 6 negative (cathode) connection and External Diode 7 positive (anode) connection External Diode 6 positive (anode) connection and External Diode 7 negative (cathode) connection Power supply TYPE OD (5V) Power AIO
10
DP4 / DN5
AIO
11 12 13 14
SMDATA SMCLK N/C DN6 / DP7
DIOD (5V) DI (5V) n/a AIO
15
DP6 / DN7
AIO
16
VDD
Power
The pin types are described below. All pins labelled (5V) are 5V tolerant:
Table 1.2 Pin Type PIN TYPE Power DI OD DIOD AIO FUNCTION Used to supply either VDD or GND to the device 5V tolerant digital input 5V tolerant Open drain digital output. Requires a pull-up resistor 5V tolerant bi-directional digital input / open-drain output. Requires a pull-up resistor. Analog input / output used for external diodes or analog inputs
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Chapter 2 Electrical Specifications
2.1 Absolute Maximum Ratings
Table 2.1 Absolute Maximum Ratings DESCRIPTION Supply Voltage (VDD) Voltage on 5V Tolerant pins Voltage on any other pin to Ground Operating Temperature Range Storage Temperature Range Lead Temperature Range Package Thermal Characteristics for QFN-16 Thermal Resistance (j-a) ESD Rating, All pins HBM 40 2000 C/W V RATING -0.3 to 4.0 -0.3 to 5.5 -0.3 to VDD +0.3 -40 to +125 -55 to +150 Refer to JEDEC Spec. J-STD020 UNIT V V V C C
Note: Stresses at or above those listed could cause permanent damage to the device. This is a stress rating only and functional operation of the device at any other condition above those indicated in the operation sections of this specification is not implied. When powering this device from laboratory or system power supplies, it is important that the Absolute Maximum Ratings not be exceeded or device failure can result. Some power supplies exhibit voltage spikes on their outputs when the AC power is switched on or off. In addition, voltage transients on the AC power line may appear on the DC output. If this possibility exists, it is suggested that a clamp circuit be used.
2.2
Electrical Specifications
Table 2.2 Electrical Specifications VDD = 3.0V to 3.6V, TA = -40C to 125C, all typical values at TA = 27C unless otherwise noted.
CHARACTERISTIC
SYMBOL
MIN
TYP
MAX
UNITS
CONDITIONS
DC Power Supply Voltage Supply Current Supply Current VDD IDD IDD 3.0 3.3 450 900 3.6 600 1200 V uA uA 1 conversion / sec, dynamic averaging disabled 4 conversions / sec, dynamic averaging enabled
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Table 2.2 Electrical Specifications (continued) VDD = 3.0V to 3.6V, TA = -40C to 125C, all typical values at TA = 27C unless otherwise noted. CHARACTERISTIC SYMBOL MIN TYP MAX UNITS CONDITIONS
Internal Temperature Monitor Temperature Accuracy 0.25 1 2 Temperature Resolution 0.125 C C C 0C < TA < 100C -40C < TA < 125C
External Temperature Monitor Temperature Accuracy 0.25 0.5 Temperature Resolution Conversion Time all Channels Capacitive Filter Resistance Error Correction tCONV CFILTER RSERIES 0.125 190 2.2 2.7 100 1 2 C C C ms nF default settings Connected across external diode In series with DP and DN lines +40C < TDIODE < +110C 0C < TA < 110C -40C < TDIODE < 127C
TRIP_SET Measurement Decoded Temperature Accuracy TSET 0.5 C RSET = 1% resistor (see Note 2.1)
ALERT and SYS_SHDN pins Output Low Voltage Leakage Current VOL ILEAK 0.4 5 Power Up Timing First conversion ready SMBus delay tCONV_f tSMB_d 300 15 ms ms Time after power up before all channels updated with valid data Delay before SMBus communications should be sent by host V uA ISINK = 8mA powered or unpowered TA < 85C
Note 2.1
If a 1% resistor is used for RSET, then it is guaranteed to decode as shown in Table 4.1.
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2.3
SMBus Electrical Characteristics
Table 2.3 SMBus Electrical Specifications VDD = 3.0V to 3.6V, TA = -40C to 125C, all typical values are at TA = 27C unless otherwise noted.
CHARACTERISTIC
SYMBOL
MIN
TYP
MAX
UNITS
CONDITIONS
SMBus Interface Input High Voltage Input Low Voltage Input High/Low Current Hysteresis Input Capacitance Output Low Sink Current CIN IOL 8.2 VIH VIL IIH / IIL 420 5 15 SMBus Timing Clock Frequency Spike Suppression Bus free time Start to Stop Hold Time: Start Setup Time: Start Setup Time: Stop Data Hold Time Data Setup Time Clock Low Period Clock High Period Clock/Data Fall time Clock/Data Rise time Clock/Data Rise time Capacitive Load fSMB tSP tBUF tHD:STA tSU:STA tSU:STP tHD:DAT tSU:DAT tLOW tHIGH tFALL tRISE tRISE CLOAD 1.3 0.6 0.6 0.6 0.3 100 1.3 0.6 300 300 1000 400 10 400 50 kHz ns us us us us us ns us us ns ns ns pF Min = 20+0.1CLOAD ns Min = 20+0.1CLOAD ns fSMB > 100kHz Min = 20+0.1CLOAD ns fSMB < 100kHz per bus line 2.0 -0.3 VDD 0.8 5 V V uA mV pF mA SMDATA = 0.4V 5V Tolerant 5V Tolerant Powered or unpowered TA < 85C
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Chapter 3 System Management Bus Interface Protocol
3.1 System Management Bus Interface Protocol
The EMC1428 communicate with a host controller, such as an SMSC SIO, through the SMBus. The SMBus is a two-wire serial communication protocol between a computer host and its peripheral devices. A detailed timing diagram is shown in Figure 3.1.
TLOW
THIGH
THD:STA TSU:STO
SMCLK
THD:STA
TRISE
TFALL
THD:DAT
TSU:DAT
TSU:STA
SMDATA
TBUF
P
S
S - Start Condition
S
P - Stop Condition P
Figure 3.1 SMBus Timing Diagram The EMC1428 are SMBus 2.0 compatible and support Send Byte, Read Byte, Write Byte, Receive Byte, and the Alert Response Address as valid protocols as shown below. All of the below protocols use the convention in Table 3.1.
Table 3.1 Protocol Format DATA SENT TO DEVICE DATA SENT TO THE HOST
Attempting to communicate with the EMC1428 SMBus interface with an invalid slave address or invalid protocol will result in no response from the device and will not affect its register contents. Stretching of the SMCLK signal is supported, provided other devices on the SMBus control the timing.
3.2
Write Byte
The Write Byte is used to write one byte of data to the registers as shown below Table 3.2:
Table 3.2 Write Byte Protocol SLAVE ADDRESS 1001_100 REGISTER ADDRESS XXh REGISTER DATA XXh
START 0 -> 1
WR 0
ACK 0
ACK 0
ACK 0
STOP 1 -> 0
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3.3
Read Byte
The Read Byte protocol is used to read one byte of data from the registers as shown in Table 3.3.
Table 3.3 Read Byte Protocol
START SLAVE ADDRESS 1001_100 WR ACK REGISTER ADDRESS XXh ACK START SLAVE ADDRESS 1001_100 RD ACK REGISTER DATA XXh NACK STOP
0-> 1
0
0
0
0 -> 1
1
0
1
1 -> 0
3.4
Send Byte
The Send Byte protocol is used to set the internal address register pointer to the correct address location. No data is transferred during the Send Byte protocol as shown in Table 3.4.
Table 3.4 Send Byte Protocol SLAVE ADDRESS 1001_100 REGISTER ADDRESS XXh
START 0 -> 1
WR 0
ACK 0
ACK 0
STOP 1 -> 0
3.5
Receive Byte
The Receive Byte protocol is used to read data from a register when the internal register address pointer is known to be at the right location (e.g. set via Send Byte). This is used for consecutive reads of the same register as shown in Table 3.5.
Table 3.5 Receive Byte Protocol SLAVE ADDRESS 1001_100
START 0 -> 1
RD 1
ACK 0
REGISTER DATA XXh
NACK 1
STOP 1 -> 0
3.6
Alert Response Address
The ALERT output can be used as a processor interrupt or as an SMBus Alert. When it detects that the ALERT pin is asserted, the host will send the Alert Response Address (ARA) to the general address of 000_1100b. All devices with active interrupts will respond with their client address as shown in Table 3.6.
Table 3.6 Alert Response Address Protocol ALERT RESPONSE ADDRESS 0001_100
START 0 -> 1
RD 1
ACK 0
DEVICE ADDRESS 1001_100
NACK 1
STOP 1 -> 0
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The EMC1428 will respond to the ARA in the following way: 1. Send Slave Address and verify that full slave address was sent (i.e. the SMBus communication from the device was not prematurely stopped due to a bus contention event). 2. Set the MASK bit to clear the ALERT pin. APPLICATION NOTE: The ARA does not clear the Status Register and if the MASK bit is cleared prior to the Status Register being cleared, the ALERT pin will be reasserted.
3.7
SMBus Address
The EMC1428-1 devices respond to the 7-bit slave address 1001_100xb. The EMC1428-6 will respond to the 7-bit slave address 1001_101xb. Note: Other addresses are available. Contact SMSC for more information.
3.8
SMBus Timeout
The EMC1428 support SMBus Timeout. If the clock line is held low for longer than 30ms, the device will reset its SMBus protocol. This function can be disabled by clearing the TIMEOUT bit in the Conversion Rate Register (see Section 5.5).
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Chapter 4 Product Description
The EMC1428 is an SMBus temperature sensor with Hardware Critical / Thermal Shutdown support. The EMC1428 monitors up to seven (7) external diodes and one internal diode. Thermal management is performed in cooperation with a host device. This consists of the host reading the temperature data of both the external and internal temperature diodes of the EMC1428 and using that data to control the speed of one or more fans. The EMC1428 device has two levels of monitoring. The first provides a maskable ALERT signal to the host when measured temperatures meet or exceed user programmable limits. This allows the EMC1428 to be used as an independent thermal watchdog to warn the host of temperature hot spots without constant monitoring by the host. The second level of monitoring asserts the SYS_SHDN pin when the External Diode 1 temperature meets or exceeds a hardware specified threshold temperature. Additionally, any of the external diode channels can be configured to assert the SYS_SHDN pin when the measured temperature meets or exceeds user programmable limits. Because the EMC1428 automatically corrects for temperature errors due to series resistance in temperature diode lines, there is greater flexibility in where external diodes are positioned and better measurement accuracy than previously available devices without resistance error correction. As well, the automatic beta detection feature means that there is no need to program the device according to which type of diode is present. Therefore, the device can power up ready to operate for any system configuration including those diodes that require the BJT or transistor model. Figure 4.1 shows a system level block diagram of the EMC1428.
.
VDD
CPU
DP1 DN1
EMC1428
ALERT
Host
SMDATA SMCLK Optional APD
DP2 / DN3 DN2 / DP3 DP4 / DN5 DN4 / DP5 DP6 / DN7 DN6 / DP7
SMBus Interface
VDD
SYS_SHDN N/C
Optional APD
Optional APD
Precision R TRIP_SET 1% RSET
Figure 4.1 System Diagram for EMC1428
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4.1
ALERT Output
The ALERT pin is an open drain output and has two modes of operation: interrupt mode and comparator Mode. The mode of the ALERT output is selected via the ALERT / COMP bit in the Configuration Register.
4.1.1
ALERT Pin Interrupt Mode
When configured to operate in interrupt mode, the ALERT pin asserts low when an out of limit measurement (> high limit or < low limit) is detected on any diode or when a diode fault is detected. The ALERT pin will remain asserted as long as an out-of-limit condition remains. Once the out-of-limit condition has been removed, the ALERT pin will remain asserted until the appropriate status bits are cleared. Each channel is subject to the fault queue (see Section 5.14). The ALERT pin can be masked by setting the MASK bit. Once the ALERT pin has been masked, it will be de-asserted and remain de-asserted until the MASK bit is cleared by the user. Any interrupt conditions that occur while the ALERT pin is masked will update the Status Register normally. The ALERT pin is used as an interrupt signal or as an SMBus Alert signal that allows an SMBus slave to communicate an error condition to the master. One or more ALERT outputs can be hard-wired together.
4.1.2
ALERT Pin Comparator Mode
When the ALERT pin is configured to operate in comparator mode it will be asserted if any of the measured temperatures meets or exceeds the respective high limit or drops below the respective low limit. The ALERT pin will remain asserted until all temperatures drop below the corresponding high limit minus the THERM Hysteresis value. When the ALERT pin is asserted in comparator mode, the corresponding status bits will be set. Reading these bits will not clear them until the ALERT pin is deasserted. Once the ALERT pin is deasserted, the status bits will be automatically cleared. The MASK bit will not block the ALERT pin in this mode, however the individual channel masks (see Section 5.13) will prevent the respective channel from asserting the ALERT pin. In addition, each channel is subject to the fault queue (see Section 5.14).
4.2
SYS_SHDN Output
The SYS_SHDN output is asserted independently of the ALERT output and cannot be masked. If the External Diode 1 temperature exceeds the Hardware Critical / Thermal Shutdown Limit for the programmed number of consecutive measurements, then the SYS_SHDN pin is asserted. The Hardware Critical / Thermal Shutdown Limit is defined by the TRIP_SET pin as described in Section 4.3. In addition to External Diode 1 channel triggering the SYS_SHDN pin when the measured temperature exceeds to the Hardware Critical / Thermal Shutdown Limit, each of the temperature measurement channels can be configured to assert the SYS_SHDN pin when they exceed the corresponding THERM Limit. When the SYS_SHDN pin is asserted, it will not release until the External Diode 1 temperature drops below the Hardware Thermal Shutdown Limit minus 10C and all other measured temperatures drop below the THERM Limit minus the THERM Hysteresis value (when linked to SYS_SHDN). The External Diode 1 channel and any software enabled channels are subject to the fault queue such that the error must exceed the threshold for one to four consecutive measurements before the SYS_SHDN pin is asserted. Figure 4.2 shows a block diagram of the interaction between the input channels and the SYS_SHDN pin.
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In te rn a l D io d e
S /W S e t S e n s o r
. . .
S /W S e t S e n s o r
T e m p e ra tu re C o n v e rs io n a n d u p to 8 T H E R M L im it R e g is te rs
H a rd w a re T h e rm a l S h u td o w n
SM Bus T ra ffic
S o ftw a re S h u td o w n E n a b le
H /W T h e rm a l S h u td o w n S e n s o r T e m p e ra tu re C o n v e rs io n SW _SH D N
3 .3 V
SYS_SHDN H W _SH D N
T R IP _ S E T
V o lta g e C o n v e rs io n
Figure 4.2 Block Diagram of Hardware Thermal Shutdown
4.3
TRIP_SET Pin
The EMC1428's TRIP_SET pin is an input to the Critical / Thermal Shutdown logic block which sets the Critical / Thermal shutdown temperature. The system designer creates a voltage level at this input through a simple resistor connected to GND as shown in Figure 4.3. The value of this resistor is used to create an input voltage on the TRIP_SET pin which is translated into a temperature ranging from 65C to 127C as enumerated in Table 4.1.
APPLICATION NOTE: Current only flows when the TRIP_SET pin is being monitored. At all other times, the internal reference voltage is removed and the TRIP_SET pin will be pulled down to ground. APPLICATION NOTE: The TRIP_SET pin circuitry is designed to use a 1% resistor externally. Using a 1% resistor will result in the Thermal / Critical Shutdown temperature being decoded correctly. If a 5% resistor is used, then the Thermal / Critical Shutdown temperature may be decoded with as much as 1C error. APPLICATION NOTE: Note that an open condition on the TRIP_SET pin will be decoded as a minimum temperature threshold level.
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EMC1428
Buffer Precision Resistor ADC 1% VSET Resistor 0.1uF (optional) Reference Voltage
Figure 4.3 Vset Circuit
Table 4.1 VTRIP Resistor Settings TEMP (C) 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 RSET () 0.0 28.7 48.7 69.8 90.9 113.0 137.0 158.0 182.0 210.0 237.0 261.0 294.0 324.0 348.0 383.0 412.0 TEMP (C) 97 98 99 100 101 102 103 104 105 106 107 108 108 110 111 112 113 RSET () 1240.0 1330.0 1400.0 1500.0 1580.0 1690.0 1820.0 1960.0 2050.0 2210.0 2370.0 2550.0 2740.0 2940.0 3160.0 3480.0 3740.0
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Table 4.1 VTRIP Resistor Settings (continued) TEMP (C) 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 RSET () 453.0 487.0 523.0 562.0 604.0 649.0 698.0 750.0 787.0 845.0 909.0 953.0 1020.0 1100.0 1150.0 TEMP (C) 114 115 116 117 118 119 120 121 122 123 124 125 126 127 65 RSET () 4120.0 4530.0 4990.0 5490.0 6040.0 6810.0 7870.0 9090.0 10700.0 12700.0 15800.0 20500.0 29400.0 49900.0 Open
4.4
Consecutive Alerts
The EMC1428 contains multiple consecutive alert counters. One set of counters applies to the ALERT pin and the second set of counters applies to the SYS_SHDN pin. Each temperature measurement channel has a separate consecutive alert counter for each of the interrupt conditions (High, Low, Diode fault). All counters are user programmable and determine the number of consecutive measurements that a temperature channel(s) must be out-of-limit or reporting a diode fault before the corresponding status bit is set or pin is asserted. See Section 5.14 for more details on the consecutive alert function.
4.5
Temperature Monitoring
The EMC1428 can monitor the temperature of up to seven (7) externally connected diodes as well as the internal or ambient temperature. Each channel is configured with the following features enabled or disabled based on user settings and system requirements.
4.5.1
Resistance Error Correction
The EMC1428 includes active Resistance Error Correction to remove the effect of up to 100 ohms of series resistance. Without this automatic feature, voltage developed across the parasitic resistance in the remote diode path causes the temperature to read higher than the true temperature is. The error induced by parasitic resistance is approximately +0.7C per ohm. Sources of series resistance include bulk resistance in the remote temperature transistor junctions, series resistance in the CPU, and resistance in the printed circuit board traces and package leads. Resistance error correction in the EMC1428 eliminates the need to characterize and compensate for parasitic resistance in the remote diode path.
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4.5.2
Beta Compensation
The forward current gain, or beta, of a transistor is not constant as emitter currents change. As well, it is not constant over changes in temperature. The variation in beta causes an error in temperature reading that is proportional to absolute temperature. Compensating for this error is also known as implementing the BJT or transistor model for temperature measurement. For discrete transistors configured with the collector and base shorted together, the beta is generally sufficiently high such that the percent change in beta variation is very small. For example, a 10% variation in beta for two forced emitter currents with a transistor whose ideal beta is 50 would contribute approximately 0.25C error at 100C. However for substrate transistors where the base-emitter junction is used for temperature measurement and the collector is tied to the substrate, the proportional beta variation will cause large error. For example, a 10% variation in beta for two forced emitter currents with a transistor whose ideal beta is 0.5 would contribute approximately 8.25C error at 100C. The Beta Compensation circuitry in the EMC1428 corrects for this beta variation to eliminate any error which would normally be induced. It automatically detects the appropriate beta setting to use.
4.5.3
Digital Averaging
To reduce the effect of noise and temperature spikes on the reported temperature, all of the external diode channels use digital averaging. This averaging acts as a running average using the previous four measured values. The default setting is to have digital averaging disabled for all channels. It can be enabled for each channel individually by the Filter Control Register (see Section 5.24).
4.5.4
"Hottest Of" Comparison
At the end of every measurement cycle, the EMC1428 compares all of the user selectable External Diode channels to determine which of these channels is reporting the hottest temperature. The hottest temperature is stored in the Hottest Temperature Registers and the appropriate status bit in the Hottest Status Register is set. As an optional feature, the EMC1428 can also flag an event if the hottest temperature channel changes. For example, suppose that External Diode channels 1, 3, and 4 are programmed to be compared in the "Hottest Of" Comparison. If the External Diode 1 channel reports the hottest temperature of the three, its temperature is copied into the Hottest Temperature Registers (in addition to the External Diode 1 Temperature registers) and it is flagged in the Hottest Status bit. If, on the next measurement, the External Diode 3 channel temperature has increased such that it is now the hottest temperature, the EMC1428 can flag this event as an interrupt condition and assert the ALERT pin.
4.5.5
Conversion Rates
The EMC1428 may be configured for different conversion rates based on the system requirements. The conversion rate is configured as described in Section 5.5. The default conversion rate is 4 conversions per second. Other available conversion rates are shown in Table 5.7.
4.5.6
Dynamic Averaging
Dynamic averaging causes the EMC1428 to measure the external diode channels for an extended time based on the selected conversion rate. This functionality can be disabled for increased power savings at the lower conversion rates (see Section 5.5). When dynamic averaging is enabled, the device will automatically adjust the sampling and measurement time for the external diode channels. This allows the device to average 2x or 4x longer than the normal 11 bit operation (nominally 21ms per channel) while still maintaining the selected conversion rate. The benefits of dynamic averaging are improved noise rejection due to the longer integration time as well as less random variation of the temperature measurement. When enabled, the dynamic averaging will affect the average supply current based on the chosen conversion rate as shown in Table 4.2 for EMC1428.
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Table 4.2 Supply Current vs. Conversion Rate for EMC1428 AVERAGE SUPPLY CURRENT CONVERSION RATE DYNAMIC AVERAGING ENABLED (DEFAULT) 715uA 750uA 900uA 950uA AVERAGING FACTOR (BASED ON 11-BIT OPERATION) DYNAMIC AVERAGING ENABLED (DEFAULT) 4x 2x 1x 0.5x DYNAMIC AVERAGING DISABLED 1x 1x 1x 0.5x
DYNAMIC AVERAGING DISABLED 450uA 550uA 815uA 950uA
1 / sec 2 / sec 4 / sec (default) Continuous (see Table 5.8)
4.6
Diode Connections
The diode connection for the External Diode 1 channel is determined based on the selected device. For the EMC1428, this channel can support a diode-connected transistor (such as a 2N3904) or a substrate transistor (such as those found in an CPU or GPU) as shown in Figure 4.4. Anti-parallel diodes are not supported on the External Diode 1 channel.
to DP to DN
to DP
to DP
to DN Local Ground Typical remote substrate transistor i.e. CPU substrate PNP Typical remote discrete PNP transistor i.e. 2N3906
Figure 4.4 Diode Connections
to DN
Typical remote discrete NPN transistor i.e. 2N3904
4.6.1
Diode Faults
The EMC1428 actively detects an open and short condition on each measurement channel. When a diode fault is detected, the temperature data MSByte is forced to a value of 80h and the FAULT bit is set in the Status Register. When an external diode channel is configured to operate in APD mode, the circuitry will detect independent open fault conditions, however a short condition will be shared between the APD channels.
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Chapter 5 Register Description
The registers shown in Table 5.1 are accessible through the SMBus. An entry of `-' indicates that the bit is not used and will always read `0'.
Table 5.1 Register Set in Hexadecimal Order REGISTER ADDRESS 00h 01h 02h 03h DEFAULT VALUE 00h 00h 00h 00h
R/W R R R-C R/W
REGISTER NAME Internal Diode Data High Byte External Diode 1 Data High Byte Status Configuration
FUNCTION Stores the integer data for the Internal Diode Stores the integer data for the External Diode 1 Stores the status bits for the Internal Diode and External Diodes Controls the general operation of the device (mirrored at address 09h) Controls the conversion rate for updating temperature data (mirrored at address 0Ah) Stores the 8-bit high limit for the Internal Diode (mirrored at address 0Bh) Stores the 8-bit low limit for the Internal Diode (mirrored at address 0Ch) Stores the integer portion of the high limit for the External Diode 1 (mirrored at register 0Dh) Stores the integer portion of the low limit for the External Diode 1 (mirrored at register 0Eh) Controls the general operation of the device (mirrored at address 03h) Controls the conversion rate for updating temperature data (mirrored at address 04h) Stores the 8-bit high limit for the Internal Diode (mirrored at address 05h) Stores the 8-bit low limit for the Internal Diode (mirrored at address 06h) Stores the integer portion of the high limit for the External Diode 1 (mirrored at register 07h)
PAGE Page 27 Page 27 Page 28 Page 29
04h
R/W
Conversion Rate
06h (4/sec) 55h (85C) 00h (0C) 55h (85C) 00h (0C) 00h
Page 29
05h
R/W
Internal Diode High Limit Internal Diode Low Limit External Diode 1 High Limit High Byte External Diode 1 Low Limit High Byte Configuration
Page 30
06h
R/W
Page 30
07h
R/W
Page 30
08h
R/W
Page 30
09h
R/W
Page 29
0Ah
R/W
Conversion Rate
06h (4/sec) 55h (85C) 00h (0C) 55h (85C)
Page 29
0Bh
R/W
Internal Diode High Limit Internal Diode Low Limit External Diode 1 High Limit High Byte
Page 30
0Ch
R/W
Page 30
0Dh
R/W
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Table 5.1 Register Set in Hexadecimal Order (continued) REGISTER ADDRESS 0Eh DEFAULT VALUE 00h (0C) 00h 00h 00h 55h (85C) 00h (0C) 00h 00h 55h (85C) 55h (85C) 00h
R/W R/W
REGISTER NAME External Diode 1 Low Limit High Byte External Diode 1 Data Low Byte External Diode 1 High Limit Low Byte External Diode 1 Low Limit Low Byte External Diode 2 High Limit High Byte External Diode 2 Low Limit High Byte External Diode 2 High Limit Low Byte External Diode 2 Low Limit Low Byte External Diode 1 THERM Limit External Diode 2 THERM Limit External Diode Fault
FUNCTION Stores the integer portion of the low limit for the External Diode 1 (mirrored at register 08h) Stores the fractional data for the External Diode 1 Stores the fractional portion of the high limit for the External Diode 1 Stores the fractional portion of the low limit for the External Diode 1 Stores the integer portion of the high limit for External Diode 2 Stores the integer portion of the low limit for External Diode 2 Stores the fractional portion of the high limit External Diode 2 Stores the fractional portion of the low limit for External Diode 2 Stores the 8-bit critical temperature limit for the External Diode 1 Stores the 8-bit critical temperature limit for External Diode 2 Stores status bits indicating which external diode detected a diode fault Voltage measured on the TRIP_SET pin to determine the Critical / Thermal shutdown threshold Controls which software channels, if any, are linked to the SYS_SHDN pin When read, returns the selected Hardware Thermal Shutdown Limit Controls the masking of individual channels Stores the 8-bit critical temperature limit for the Internal Diode Stores the 8-bit hysteresis value that applies to all THERM limits Controls the number of out-of-limit conditions that must occur before the status bit is asserted Stores the integer data for External Diode 2
23
PAGE Page 30
10h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh
R R/W R/W R/W R/W R/W R/W R/W R/W R-C
Page 27 Page 30 Page 30 Page 30 Page 30 Page 30 Page 30 Page 33 Page 33 Page 34
1Ch
R
TRIP_SET Voltage
00h
Page 35
1Dh
R/W
SYS_SHDN Configuration Hardware Thermal Shutdown Limit Interrupt Mask Register Internal Diode THERM Limit THERM Hysteresis Consecutive ALERT
00h
Page 35
1Eh 1Fh 20h 21h 22h
R R/W R/W R/W R/W
N/A F0h 55h (85C) 0Ah (10C) 70h
Page 36 Page 36 Page 33 Page 33 Page 37
23h
R
External Diode 2 Data High Byte
00h
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Table 5.1 Register Set in Hexadecimal Order (continued) REGISTER ADDRESS 24h 25h DEFAULT VALUE 00h 08h
R/W R R
REGISTER NAME External Diode 2 Data Low Byte External Diode 1 Beta Configuration External Diode 2 Beta Configuration Internal Diode Data Low Byte External Diode 3 High Byte External Diode 3 Low Byte External Diode 3 High Limit High Byte External Diode 3 Low Limit High Byte External Diode 3 High Limit Low Byte External Diode 3 Low Limit Low Byte External Diode 3 THERM Limit Hottest Diode High Byte Hottest Diode Low Byte Hottest Status High Limit Status Low Limit Status THERM Limit Status REC Configuration Hottest Config
FUNCTION Stores the fractional data for External Diode 2 Stores the Beta Compensation circuitry settings for External Diode 1 Stores the Beta Compensation circuitry settings for External Diode 2 Stores the fractional data for the Internal Diode Stores the integer data for External Diode 3 Stores the fractional data for External Diode 3 Stores the integer portion of the high limit for External Diode 3 Stores the integer portion of the low limit for External Diode 3 Stores the fractional portion of the high limit for External Diode 3 Stores the fractional portion of the low limit for External Diode 3 Stores the 8-bit critical temperature limit for External Diode 3 Stores the integer data for the hottest temperature Stores the fractional data for the hottest temperature Status bits indicating which external diode is hottest Status bits for the High Limits Status bits for the Low Limits Status bits for the THERM Limits Controls REC for all channels Controls which external diode channels are used in the "hottest of "comparison Controls which channels are enabled Controls the digital filter setting for the External Diode 1 channel
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26h
R/W
08h
Page 38
29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh 30h 32h 33h 34h 35h 36h 37h 39h 3Ah
R R R R/W R/W R/W R/W R/W R R R-C R-C R-C R R/W R/W
00h 00h 00h 55h (85C) 00h (0C) 00h 00h 55h (85C) 00h 00h 00h 00h 00h 00h 00h 00h
Page 27 Page 27 Page 27 Page 30 Page 30 Page 30 Page 30 Page 33 Page 39 Page 39 Page 40 Page 40 Page 41 Page 41 Page 42 Page 42
3Bh 40h
R/W R/W
Channel Config Filter Control
00h 00h
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Table 5.1 Register Set in Hexadecimal Order (continued) REGISTER ADDRESS 41h 42h 43h 44h 45h 46h 47h 48h 50h DEFAULT VALUE 00h 00h 00h 00h 00h 00h 00h 00h 55h (85C) 00h (0C) 00h
R/W R R R R R R R R R/W
REGISTER NAME External Diode 4 Data High Byte External Diode 4 Data Low Byte External Diode 5 Data High Byte External Diode 5 Data Low Byte External Diode 6 Data High Byte External Diode 6 Data Low Byte External Diode 7 Data High Byte External Diode 7 Data Low Byte External Diode 4 High Limit High Byte External Diode 4 Low Limit High Byte External Diode 4 HIgh Limit Low Byte External Diode 4 Low Limit Low Byte External Diode 5 High Limit High Byte External Diode 5 Low Limit High Byte External Diode 5 HIgh Limit Low Byte External Diode 5 Low Limit Low Byte External Diode 6 High Limit High Byte
FUNCTION Stores the integer data for the External Diode 4 channel Stores the fractional data for the External Diode 4 channel Stores the integer data for the External Diode 5 channel Stores the fractional data for the External Diode 5 channel Stores the integer data for the External Diode 6 channel Stores the fractional data for the External Diode 6 channel Stores the integer data for the External Diode 7 channel Stores the fractional data for the External Diode 7 channel Stores the integer data for the high limit for the External Diode 4 channel Stores the integer data for the low limit for the External Diode 4 channel Stores the fractional data for the low limit for the External Diode 4 channel Stores the fractional data for the low limit for the External Diode 4 channel Stores the integer data for the high limit for the External Diode 5 channel Stores the integer data for the low limit for the External Diode 5 channel Stores the fractional data for the low limit for the External Diode 5 channel Stores the fractional data for the low limit for the External Diode 5 channel Stores the integer data for the high limit for the External Diode 6 channel
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51h
R/W
Page 30
52h
R/W
Page 30
53h
R/W
00h
Page 30
54h
R/W
55h (85C) 00h (0C) 00h
Page 30
55h
R/W
Page 30
56h
R/W
Page 30
57h
R/W
00h
Page 30
58h
R/W
55h (85C)
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Table 5.1 Register Set in Hexadecimal Order (continued) REGISTER ADDRESS 59h DEFAULT VALUE 00h (0C) 00h (0C) 00h (0C) 55h (85C) 00h (0C) 00h
R/W R/W
REGISTER NAME External Diode 6 Low Limit High Byte External Diode 6 HIgh Limit Low Byte External Diode 6 Low Limit Low Byte External Diode 7 High Limit High Byte External Diode 7 Low Limit High Byte External Diode 7 HIgh Limit Low Byte External Diode 7 Low Limit Low Byte External Diode 4 THERM Limit External Diode 5 THERM Limit External Diode 6 THERM Limit External Diode 7 THERM Limit External Diode 4 Beta Configuration External Diode 6 Beta Configuration Product ID EMC1428 Manufacturer ID Revision
FUNCTION Stores the integer data for the low limit for the External Diode 6 channel Stores the fractional data for the low limit for the External Diode 6 channel Stores the fractional data for the low limit for the External Diode 6 channel Stores the integer data for the high limit for the External Diode 7 channel Stores the integer data for the low limit for the External Diode 7 channel Stores the fractional data for the low limit for the External Diode 7 channel Stores the fractional data for the low limit for the External Diode 7 channel Stores the 8-bit critical temperature limit for External Diode 4 Stores the 8-bit critical temperature limit for External Diode 5 Stores the 8-bit critical temperature limit for External Diode 6 Stores the 8-bit critical temperature limit for External Diode 7 Stores the Beta Compensation circuitry settings for External Diode 4 Stores the Beta Compensation circuitry settings for External Diode 6 Stores a fixed value that identifies each product Stores a fixed value that represents SMSC Stores a fixed value that represents the revision number
PAGE Page 30
5Ah
R/W
Page 30
5Bh
R/W
Page 30
5Ch
R/W
Page 30
5Dh
R/W
Page 30
5Eh
R/W
Page 30
5Fh
R/W
00h
Page 30
64h 65h 66h 67h 71h
R/W R/W R/W R/W R/W
55h (85C) 55h (85C) 55h (85C) 55h (85C) 08h
Page 30 Page 30 Page 30 Page 30 Page 38
72h
R/W
08h
Page 38
FDh FEh FFh
R R R
29h 5Dh 01h
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5.1
Data Read Interlock
When any temperature channel high byte register is read, the corresponding low byte is copied into an internal `shadow' register. The user is free to read the low byte at any time and be guaranteed that it will correspond to the previously read high byte. Regardless if the low byte is read or not, reading from the same high byte register again will automatically refresh this stored low byte data.
5.2
Temperature Data Registers
Table 5.2 Temperature Data Registers
ADDR 00h 29h 01h 10h 23h 24h 2Ah 2Bh 41h 42h 43h 44h 45h 46h 47h 48h
R/W R R R R R R R R R R R R R R R R
REGISTER Internal Diode High Byte Internal Diode Low Byte External Diode 1 High Byte External Diode 1 Low Byte External Diode 2 High Byte External Diode 2 Low Byte External Diode 3 High Byte External Diode 3 Low Byte External Diode 4 High Byte External Diode 4 Low Byte External Diode 5 High Byte External Diode 5 Low Byte External Diode 6 High Byte External Diode 6 Low Byte External Diode 7 High Byte External Diode 7 Low Byte
B7 Sign 0.5 Sign 0.5 Sign 0.5 Sign 0.5 Sign 0.5 Sign 0.5 Sign 0.5 Sign 0.5
B6 64 0.25 64 0.25 64 0.25 64 0.25 64 0.25 64 0.25 64 0.25 64 0.25
B5 32 0.125 32 0.125 32 0.125 32 0.125 32 0.125 32 0.125 32 0.125 32 0.125
B4 16 16 16 16 16 16 16 16 -
B3 8 8 8 8 8 8 8 8 -
B2 4 4 4 4 4 4 4 4 -
B1 2 2 2 2 2 2 2 2 -
B0 1 1 1 1 1 1 1 1 -
DEFAULT 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h
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All temperatures are stored as an 11-bit value with the high byte representing the integer value and the low byte representing the fractional value left justified to occupy the MSBits. The data format is standard 2's complement from -64C to 127.875C as shown in Table 5.3.
Table 5.3 Temperature Data Format HEX (AS READ BY REGISTERS) 80_00h C0_00h C0_20h FF_00h FF_E0h 00_00h 00_20h 01_00h 3F_00h 40_00h 7F_00h 7F_E0h
TEMPERATURE (C) Diode Fault -64 -63.875 -1 -0.125 0 0.125 1 63 64 127 127.875
BINARY 1000_0000_000b 1100_0000_000b 1100_0000_001b 1111_1111_000b 1111_1111_111b 0000_0000_000b 0000_0000_001b 0000_0001_000b 0011_1111_000b 0100_0000_000b 0111_1111_000b 0111_1111_111b
5.3
Status Register
Table 5.4 Status Register
ADDR 02h
R/W R
REGISTER Status
B7 BUSY
B6 HOT TEST
B5 -
B4 HIGH
B3 LOW
B2 FAULT
B1 SW_ SYS
B0 HWSD
DEFAULT 00h
The Status Register reports general error conditions. To identify specific channels, refer to Section 5.9, Section 5.18, Section 5.19, and Section 5.20. The individual Status Register bits (except HOTTEST) are cleared when the appropriate High Limit, Low Limit, or THERM Limit register has been read or cleared. Bit 7 - BUSY - This bit indicates that the ADC is currently converting. This bit does not cause the ALERT pin to be asserted. Bit 6 - HOTTEST - This bit is set if the REM_HOT bit (see Section 5.23) is set and the hottest channel changes. This bit is cleared when the register is read. Bit 4 - HIGH - This bit is set when any of the temperature channels meets or exceeds its programmed high limit. See the High Limit Status Register for specific channel information (Section 5.18). When set, this bit will assert the ALERT pin. Bit 3 - LOW - This bit is set when any of the temperature channels drops below its programmed low limit. See the Low Limit Status Register for specific channel information (Section 5.19). When set, this bit will assert the ALERT pin.
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Bit 2 - FAULT - This bit is asserted when a diode fault is detected on any of the external diode channels. See the External Diode Fault Register for specific channel information (Section 5.9). When set, this bit will assert the ALERT pin. Bit 1 - SW_SYS - This bit is set when any of the external diode channels meet or exceed the respected THERM Limits. See the Therm Status Register for specific channel information (Section 5.20) Bit 0 - HWSD - This bit is set when the External Diode 1 Temperature meets or exceeds the Hardware Critical / Thermal Shutdown Limit. When set, this bit will assert the SYS_SHDN pin. This bit is cleared when read if the SYS_SHDN pin has been released.
5.4
Configuration Register
Table 5.5 Configuration Register
ADDR 03h 09h
R/W R/W
REGISTER Config
B7 MASK_ ALL
B6 -
B5 ALERT /COMP
B4 -
B3 -
B2 -
B1 DAVG_ DIS
B0 -
DEFAULT 00h
The Configuration Register controls the basic operation of the device. This register is fully accessible at either address. Bit 7 - MASK_ALL - Masks the ALERT pin from asserting. `0' (default) - The ALERT pin is not masked. If any of the appropriate status bits are set the ALERT pin will be asserted. `1' - The ALERT pin is masked. It will not be asserted for any interrupt condition. The Status Registers will be updated normally. Bit 5 - ALERT/COMP - Controls the operation of the ALERT pin. `0' (default) - The ALERT pin acts as described in Section 4.1.1. `1' - The ALERT pin acts in comparator mode as described in Section 4.1.2. In this mode the MASK_ALL bit is ignored. Bit 1 - DAVG_DIS - Disables the dynamic averaging feature on all temperature channels (see Section 4.5.6). `0' (default) - The dynamic averaging feature is enabled. All temperature channels will be converted with an averaging factor that is based on the conversion rate as shown in Table 4.2. `1' - The dynamic averaging feature is disabled. All temperature channels will be converted with a maximum averaging factor of 1x (equivalent to 11-bit conversion). For higher conversion rates (i.e. more conversions per second), this averaging factor will be reduced as shown in Table 4.2.
5.5
Conversion Rate Register
Table 5.6 Conversion Rate Register
ADDR 04h 0Ah
R/W R/W
REGISTER Conversion Rate
B7 -
B6 -
B5 -
B4 -
B3
B2
B1 CONV[2:0]
B0
DEFAULT 06h (4/sec)
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Datasheet
The Conversion Rate Register controls how often the temperature measurement channels are updated and compared against the limits. This register is fully accessible at either address. Bits 3-0 - CONV[3:0] - Determines the conversion rate as shown in Table 5.7.
Table 5.7 Conversion Rate CONV[2:0] 2 1 1 1 1 1 0 0 1 1 All Others 0 0 1 0 1 CONVERSIONS / SECOND 1 2 4 (default) Continuous 4
The actual conversion rate for Continuous conversions will depend on the number of diode channels enabled and is shown in Table 5.8.
Table 5.8 Maximum Conversion Rate Per Temperature Channels NUMBER OF EXTERNAL DIODE CHANNELS 4 5 6 7 MAX CONVERSION RATE 12 / sec 11 / sec 10 / sec 9 / sec
5.6
Limit Registers
Table 5.9 Temperature Limit Registers
ADDR. 05h 0Bh 06h 0Ch 07h 0Dh
R/W R/W
REGISTER Internal Diode High Limit Internal Diode Low Limit External Diode 1 High Limit High Byte
B7 Sign
B6 64
B5 32
B4 16
B3 8
B2 4
B1 2
B0 1
DEFAULT 55h (85C) 00h (0C) 55h (85C)
R/W
Sign
64
32
16
8
4
2
1
R/W
Sign
64
32
16
8
4
2
1
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Table 5.9 Temperature Limit Registers (continued) ADDR. 13h R/W R/W REGISTER External Diode 1 High Limit Low Byte External Diode 1 Low Limit High Byte External Diode 1 Low Limit Low Byte External Diode 2 High Limit High Byte External Diode 2 Low Limit High Byte External Diode 2 High Limit Low Byte External Diode 2 Low Limit Low Byte External Diode 3 High Limit High Byte External Diode 3 Low Limit High Byte External Diode 3 High Limit Low Byte External Diode 3 Low Limit Low Byte External Diode 4 High Limit High Byte B7 0.5 B6 0.25 B5 0.125 B4 B3 B2 B1 B0 DEFAULT 00h
08h 0Eh 14h
R/W
Sign
64
32
16
8
4
2
1
00h (0C)
R/W
0.5
0.25
0.125
-
-
-
-
-
00h
15h
R/W
Sign
64
32
16
8
4
2
1
55h (85C)
16h
R/W
Sign
64
32
16
8
4
2
1
00h (0C)
17h
R/W
0.5
0.25
0.125
-
-
-
-
-
00h
18h
R/W
0.5
0.25
0.125
-
-
-
-
-
00h
2Ch
R/W
Sign
64
32
16
8
4
2
1
55h (85C)
2Dh
R/W
Sign
64
32
16
8
4
2
1
00h (0C)
2Eh
R/W
0.5
0.25
0.125
-
-
-
-
-
00h
2Fh
R/W
0.5
0.25
0.125
-
-
-
-
-
00h
50h
R/W
Sign
64
32
16
8
4
2
1
55h (85C)
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Table 5.9 Temperature Limit Registers (continued) ADDR. 51h R/W R/W REGISTER External Diode 4 Low Limit High Byte External Diode 4 High Limit Low Byte External Diode 4 Low Limit Low Byte External Diode 5 High Limit High Byte External Diode 5 Low Limit High Byte External Diode 5 High Limit Low Byte External Diode 5 Low Limit Low Byte External Diode 6 High Limit High Byte External Diode 6 Low Limit High Byte External Diode 6 High Limit Low Byte External Diode 6 Low Limit Low Byte External Diode 7 High Limit High Byte B7 Sign B6 64 B5 32 B4 16 B3 8 B2 4 B1 2 B0 1 DEFAULT 00h (0C)
52h
R/W
0.5
0.25
0.125
-
-
-
-
-
00h
53h
R/W
0.5
0.25
0.125
-
-
-
-
-
00h
54h
R/W
Sign
64
32
16
8
4
2
1
55h (85C)
55h
R/W
Sign
64
32
16
8
4
2
1
00h (0C)
56h
R/W
0.5
0.25
0.125
-
-
-
-
-
00h
57h
R/W
0.5
0.25
0.125
-
-
-
-
-
00h
58h
R/W
Sign
64
32
16
8
4
2
1
55h (85C)
59h
R/W
Sign
64
32
16
8
4
2
1
00h (0C)
5Ah
R/W
0.5
0.25
0.125
-
-
-
-
-
00h
5Bh
R/W
0.5
0.25
0.125
-
-
-
-
-
00h
5Ch
R/W
Sign
64
32
16
8
4
2
1
55h (85C)
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Table 5.9 Temperature Limit Registers (continued) ADDR. 5Dh R/W R/W REGISTER External Diode 7 Low Limit High Byte External Diode 7 High Limit Low Byte External Diode 7 Low Limit Low Byte B7 Sign B6 64 B5 32 B4 16 B3 8 B2 4 B1 2 B0 1 DEFAULT 00h (0C)
5Eh
R/W
0.5
0.25
0.125
-
-
-
-
-
00h
5Fh
R/W
0.5
0.25
0.125
-
-
-
-
-
00h
The device contains both high and low limits for all temperature channels. If the measured temperature meets or exceeds the high limit, then the corresponding status bit is set and the ALERT pin is asserted. Likewise, if the measured temperature is less than the low limit, the corresponding status bit is set and the ALERT pin is asserted. The limit registers with multiple addresses are fully accessible at either address.
5.7
Therm Hysteresis Register
Table 5.10 Therm Hysteresis Register
ADDR. 21h
R/W R/W
REGISTER THERM Hysteresis
B7 -
B6 64
B5 32
B4 16
B3 8
B2 4
B1 2
B0 1
DEFAULT 0Ah (10C)
The THERM Hysteresis is used in conjunction with the THERM Limit Registers to assert the SYS_SHDN pin. In addition, the THERM Hysteresis Register is used with the High Limit Registers when the ALERT pin is configured to act as a comparator (see Section 4.1.2).
5.8
Therm Limit Registers
Table 5.11 Therm Limit Registers
ADDR. 19h
R/W R/W
REGISTER External Diode 1 THERM Limit External Diode 2 THERM Limit Internal Diode THERM Limit
B7 Sign
B6 64
B5 32
B4 16
B3 8
B2 4
B1 2
B0 1
DEFAULT 55h (85C) 55h (85C) 55h (85C)
1Ah
R/W
Sign
64
32
16
8
4
2
1
20h
R/W
Sign
64
32
16
8
4
2
1
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Table 5.11 Therm Limit Registers (continued) ADDR. 30h R/W R/W REGISTER External Diode 3 THERM Limit External Diode 4 THERM Limit External Diode 5 THERM Limit External Diode 6 THERM Limit External Diode 7 THERM Limit B7 Sign B6 64 B5 32 B4 16 B3 8 B2 4 B1 2 B0 1 DEFAULT 55h (85C) 55h (85C) 55h (85C) 55h (85C) 55h (85C)
64h
R/W
Sign
64
32
16
8
4
2
1
65h
R/W
Sign
64
32
16
8
4
2
1
66h
R/W
Sign
64
32
16
8
4
2
1
67h
R/W
Sign
64
32
16
8
4
2
1
The THERM Limit Registers are used to set the threshold for the software inputs to the Critical / Thermal Shutdown circuitry. If the measured channel is linked to the Critical / Thermal Shutdown circuitry and meets or exceeds this limit, then the SYS_SHDN pin will be asserted.
5.9
External Diode Fault Register
Table 5.12 External Diode Fault Register
ADDR 1Bh
R/W R-C
REGISTER External Diode Fault
B7 E7FLT
B6 E6FLT
B5 E5FLT
B4 E4FLT
B3 E3FLT
B2 E2FLT
B1 E1FLT
B0 -
DEFAULT 00h
The External Diode Fault Register indicates which of the external diodes caused the FAULT bit in the Status Register to be set. These bits are cleared when read if the error condition has been removed. Bit 7 - E7FLT - This bit is set if the External Diode 7 channel reported a diode fault. Bit 6 - E6FLT - This bit is set if the External Diode 6 channel reported a diode fault. Bit 5 - E5FLT - This bit is set if the External Diode 5 channel reported a diode fault. Bit 4 - E4FLT - This bit is set if the External Diode 4 channel reported a diode fault. Bit 3 - E3FLT - This bit is set if the External Diode 3 channel reported a diode fault. Bit 2 - E2FLT - This bit is set if the External Diode 2 channel reported a diode fault. Bit 1 - E1FLT - This bit is set if the External Diode 1 channel reported a diode fault.
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5.10
TRIP_SET Reading Register
Table 5.13 TRIP_SET Reading Register
ADDR 1Ch
R/W R
REGISTER TRIP_SET Reading
B7 752.9
B6 376.5
B5 188.2
B4 94.12
B3 47.1
B2 23.53
B1 11.76
B0 5.88
DEFAULT 00h
The TRIP_SET Reading Register stores the voltage measured on the TRIP_SET pin. The bit weighting represents mV above 0V.
5.11
Software Thermal Shutdown Configuration Register
Table 5.14 Software Thermal Shutdown Configuration Register
ADDR 1Dh
R/W R/W
REGISTER Software Thermal Shutdown Configuration
B7 E7 SYS
B6 E6 SYS
B5 E5 SYS
B4 E4 SYS
B3 E3 SYS
B2 E2 SYS
B1 E1 SYS
B0 INT SYS
DEFAULT 00h
The Software Thermal Shutdown Configuration Register controls whether any of the software channels will assert the SYS_SHDN pin. If a channel is enabled, the temperature is compared against the corresponding THERM Limit. If the measured temperature meets or exceeds the THERM Limit, then the SYS_SHDN pin is asserted. This functionality is in addition to the Hardware Shutdown circuitry. Bits 7-1 - ExSYS - configures the External Diode X channel to assert the SYS_SHDN pin based on it's respective THERM Limit (see Section 5.20 for details on the ExTHERM status bits). `0' (default) - the External Diode X channel is not linked to the SYS_SHDN pin. If the temperature meets or exceeds it's THERM Limit, the ExTHERM status bit is set but the SYS_SHDN pin is not asserted. `1' - the External Diode X channel is linked to the SYS_SHDN pin. If the temperature meets or exceeds it's THERM Limit, the ExTHERM status bit is set and the SYS_SHDN pin is asserted. It will remain asserted until the temperature drops below it's THERM Limit minus the THERM Hysteresis. Bit 0 - INTSYS - configures the Internal Diode channel to assert the SYS_SHDN pin based on it's respective THERM Limit (see Section 5.20 for details on the ITHERM status bit). `0' (default) - the Internal Diode channel is not linked to the SYS_SHDN pin. If the temperature meets or exceeds it's THERM Limit, the ITHERM status bit is set but the SYS_SHDN pin is not asserted. `1' - the Internal Diode channel is linked to the SYS_SHDN pin. If the temperature meets or exceeds it's THERM Limit, the ITHERM status bit is set and the SYS_SHDN pin is asserted. It will remain asserted until the temperature drops below it's THERM Limit minus the THERM Hysteresis.
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1C Multiple Temperature Sensor with HW Thermal Shutdown & Hottest of Thermal Zones
Datasheet
5.12
Hardware Critical / Thermal Shutdown Limit Register
Table 5.15 Hardware Thermal Shutdown Limit Register
ADDR 1Eh
R/W R
REGISTER Hardware Thermal Shutdown Limit
B7 -
B6 64
B5 32
B4 16
B3 8
B2 4
B1 2
B0 1
DEFAULT N/A
This read only register returns the Hardware Thermal Shutdown Limit selected by the TRIP_SET voltage. The data represents the hardware set temperature in C. See Table 5.2 for the data format. When the External Diode 1 Temperature meets or exceeds this limit, the SYS_SHDN pin is asserted and will remain asserted until the External Diode 1 Temperature drops below this limit minus 10C.
5.13
Channel Interrupt Mask Register
Table 5.16 Channel Interrupt Mask Register
ADDR 1Fh
R/W R/W
REGISTER Channel Mask
B7 E7_ MSK
B6 E6_ MSK
B5 E5_ MSK
B4 E4_ MSK
B3 E3_ MSK
B2 E2_ MSK
B1 E1_ MSK
B0 INT_ MSK
DEFAULT F0h
The Channel Interrupt Mask Register controls individual channel masking. When a channel is masked, the ALERT pin will not be asserted when the masked channel reads a diode fault or out of limit error. The channel mask does not mask the SYS_SHDN pin. Bits 7-4 - Ex_MSK - Prevents the ALERT pin from being asserted when the External Diode X channel is out of limit or reports a diode fault. If the EXT6_APD bit is not set (see Section 5.23), then the EXT7_MSK bit is ignored. Likewise, if the EXT4_APD bit is not set, then the EXT5_MSK bit is ignored. `0' - The External Diode X channel will cause the ALERT pin to be asserted if it is out of limit or reports a diode fault. `1' (default) - The External Diode X channel will not cause the ALERT pin to be asserted if it is out of limit or reports a diode fault. Bits 3-1- Ex_MSK - Prevents the ALERT pin from being asserted when the External Diode X channel is out of limit or reports a diode fault. If the EXT2_APD bit is not set (see Section 5.23), then the EXT3_MSK bit is ignored. `0' - (default) The External Diode X channel will cause the ALERT pin to be asserted if it is out of limit or reports a diode fault. `1' - The External Diode X channel will not cause the ALERT pin to be asserted if it is out of limit or reports a diode fault. Bit 0 - INT_MSK- Prevents the ALERT pin from being asserted when the Internal Diode temperature is out of limit. `0' (default) - The Internal Diode channel will cause the ALERT pin to be asserted if it is out of limit. `1' - The Internal Diode channel will not cause the ALERT pin to be asserted if it is out of limit.
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5.14
Consecutive ALERT Register
Table 5.17 Consecutive ALERT Register
ADDR. 22h
R/W R/W
REGISTER Consecutive ALERT
B7 TIME OUT
B6 CTHE RM2
B5 CTHE RM1
B4 CTHE RM0
B3 CAL RT2
B2 CAL RT1
B1 CAL RT0
B0 -
DEFAULT 70h
The Consecutive ALERT Register determines how many times an out-of-limit error or diode fault must be detected in consecutive measurements before the interrupt status registers are asserted. Each out of limit error and diode fault condition has its own counter associated with it. Each counter is incremented whenever the corresponding channel exceeds the appropriate limit. Additionally, each counter is reset if the condition has been removed. (i.e. if External Diode 1 exceeds its high limit, it will increment the high counter. If, on the next measurement, it experiences a diode fault, the high limit counter will be reset and the diode fault counter will be incremented). When the ALERT pin is configured as an interrupt and the consecutive alert counter reaches its programmed value then the STATUS bit(s) for that channel and the error condition will be set to `1' and the ALERT pin will be asserted. Measurements will continue normally. When the ALERT pin is configured as a comparator, the consecutive alert counter will ignore diode fault and low limit errors and only increment if the measured temperature meets or exceeds the High Limit. Additionally, once the consecutive alert counter reaches the programmed limit, the ALERT pin will be asserted, but the counter will not be reset. It will remain set until the temperature drops below the High Limit minus the THERM Hysteresis value. For example, if the CALRT[2:0] bits are set for 4 consecutive alerts on an EMC1428 device, the high limits are set at 70C, and none of the channels are masked, then the status bits will be asserted after the following four measurements: 1. Internal Diode reads 71C and both external diodes read 69C. Consecutive alert counter for INT is incremented to 1. 2. Both the Internal Diode and the External Diode 1 read 71C and External Diode 2 reads 68C. Consecutive alert counter for INT is incremented to 2 and for EXT1 is set to 1. 3. The External Diode 1 reads 71C and both the Internal Diode and External Diode 2 read 69C. Consecutive alert counter for INT and EXT2 are cleared and EXT1 is incremented to 2. 4. The Internal Diode reads 71C and both external diodes read 71C. Consecutive alert counter for INT is set to 1, EXT2 is set to 1, and EXT1 is incremented to 3. 5. The Internal Diode reads 71C and both the external diodes read 71C. Consecutive alert counter for INT is incremented to 2, EXT2 is set to 2, and EXT1 is incremented to 4. The HIGH status bit are set for EXT1 and the ALERT pin is asserted. The EXT1 counter is reset to 0 and all other counters hold the last value until the next temperature measurement. Bit 7 - TIMEOUT - Determines whether the SMBus Timeout function is enabled. `0' (default) - The SMBus Timeout feature is disabled. The SMCLK line can be held low indefinitely without the device resetting its SMBus protocol. `1' - The SMBus Timeout feature is enabled. If the SMCLK line is held low for more than 30ms, then the device will reset the SMBus protocol. Bits 6-4 CTHRM[2:0] - Determines the number of consecutive measurements that must exceed the corresponding THERM Limit and Hardware Thermal Shutdown Limit before the SYS_SHDN pin is asserted. All temperature channels use this value to set the respective counters. The consecutive THERM counter is incremented whenever any of the measurements exceed the corresponding THERM Limit or if the External Diode 1 measurement meets or exceeds the Hardware Thermal Shutdown Limit.
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If the temperature drops below the THERM limit or Hardware Thermal Shutdown Limit, then the counter is reset. If the programmed number of consecutive measurements exceed the THERM Limit or Hardware Thermal Shutdown Limit, and the appropriate channel is linked to the SYS_SHDN pin, then the SYS_SHDN pin will be asserted low. Once the SYS_SHDN pin is asserted, the consecutive THERM counter will not reset until the corresponding temperature drops below the appropriate limit minus the corresponding hysteresis. The bits are decoded as shown in Table 5.18. The default setting is 4 consecutive out of limit conversions. Bits 3-1 - CALRT[2:0] - Determine the number of consecutive measurements that must have an out of limit condition or diode fault before the STATUS bits is asserted. All temperature channels use this value to set the respective counters. The bits are decoded as shown in Table 5.18. The default setting is 1 consecutive out of limit conversion. APPLICATION NOTE: If one of the fault queues is not cleared and the CALRT[2:0] (or CTHRM[2:0]) bits are updated, the update won't take affect until fault queue is cleared. All the fault queues are independent so those that are empty will be updated immediately.
Table 5.18 Consecutive Alert Settings NUMBER OF CONSECUTIVE OUT OF LIMIT MEASUREMENTS 1 (default for CALRT[2:0]) 2 3 4 (default for CTHRM[2:0]) 1 (CALRT[2:0]), 4 (CTHRM[2:0])
2 0 0 0 1
1 0 0 1 1 All Others
0 0 1 1 1
5.15
Beta Configuration Register
Table 5.19 Beta Configuration Register
ADDR. 25h
R/W R
REGISTER External Diode 1 Beta Configuration External Diode 2 Beta Configuration External Diode 4 Beta Configuration External Diode 6 Beta Configuration
B7 -
B6 -
B5 -
B4 -
B3 AUTO1
B2
B1 BETA1[2:0]
B0
DEFAULT 08h
26h
R/W
-
-
-
-
AUTO2
BETA2[2:0]
08h
71h
R/W
-
-
-
-
AUTO4
BETA4[2:0]
08h
72h
R/W
-
-
-
-
AUTO6
BETA6[2:0]
07h
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These registers are used to set the Beta Compensation factor that is used for the External Diode channels. Bit 3 - AUTOx - Enables the Beta Compensation factor autodetection function. `0' - The Beta Compensation Factor autodetection circuitry is disabled. The External Diode will always use the Beta Compensation factor set by the BETAx[2:0] bits. `1' (default) - The Beta Compensation factor autodetection circuitry is enabled. At the beginning of every conversion, the optimal Beta Compensation factor setting will be determined and applied. The BETAx[2:0] bits will be automatically updated to indicate the current setting. Bit 2-0 - BETAx[2:0] - These bits always reflect the current beta configuration settings. These bits will be updated automatically and writing to these bits will have no effect.
Table 5.20 Beta Compensation Look Up Table BETAX[2:0] 2 0 0 0 0 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 MINIMUM BETA < 0.08 < 0.111 < 0.176 < 0.29 < 0.48 < 0.9 < 2.33 Disabled
5.16
Hottest Temperature Registers
Table 5.21 Hottest Temperature Registers
ADDR 32h
R/W R
REGISTER Hottest Temperature High Byte Hottest Temperature Low Byte
B7 Sign
B6 64
B5 32
B4 16
B3 8
B2 4
B1 2
B0 1
DEFAULT 80h
33h
R
0.5
0.25
0.125
-
-
-
-
-
00h
The Hottest Temperature Registers store the measured hottest temperature of all the selected external diode channels (see Section 5.22). If no External diodes are selected then the High Byte Register will read 80h. The data format is the same as the temperature channels.
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5.17
Hottest Temperature Status Register
Table 5.22 Hottest Temperature Register
ADDR 34h
R/W R
REGISTER Hottest Temperature Status
B7 EXT7
B6 EXT6
B5 EXT5
B4 EXT4
B3 EXT3
B2 EXT2
B1 EXT1
B0 INT
DEFAULT 00h
The Hottest Temperature Status Register flags which external diode temperature is hottest. If multiple temperature channels measure the same temperature and are equal to the hottest temperature, then hottest status will be based on the measurement order. Bit 7 - EXT7 - The External Diode 7 channel is the hottest. Bit 6 - EXT6 - The External Diode 6 channel is the hottest. Bit 4 - EXT5 - The External Diode 5 channel is the hottest. Bit 3 - EXT4 - The External Diode 4 channel is the hottest. Bit 3 - EXT3 - The External Diode 3 channel is the hottest. Bit 2 - EXT2 - The External Diode 2 channel is the hottest. Bit 1 - EXT1 - The External Diode 1 channel is the hottest. Bit 0 - INT - The Internal Diode channel is the hottest.
5.18
High Limit Status Register
Table 5.23 High Limit Status Register
ADDR 35h
R/W R-C
REGISTER High Limit Status
B7 E7 HIGH
B6 E6 HIGH
B5 E5 HIGH
B4 E4 HIGH
B3 E3 HIGH
B2 E2 HIGH
B1 E1 HIGH
B0 I HIGH
DEFAULT 00h
The High Limit Status Register contains the status bits that are set when a temperature channel high limit is exceeded for a number of consecutive readings as set by the consecutive alert counts (see Section 5.14). If any of these bits are set, then the HIGH status bit in the Status Register is set. Reading from the High Limit Status Register will clear all bits if the error condition has been removed. Reading from the register will also clear the HIGH status bit in the Status Register. The ALERT pin will be set if any of these status bits are set. Bit 7 - E7HIGH - This bit is set when the External Diode 7 channel meets or exceeds its programmed high limit. Bit 6 - E6HIGH - This bit is set when the External Diode 6 channel meets or exceeds its programmed high limit. Bit 5 - E5HIGH - This bit is set when the External Diode 5 channel meets or exceeds its programmed high limit. Bit 4 - E4HIGH - This bit is set when the External Diode 4 channel meets or exceeds its programmed high limit.
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Bit 3 - E3HIGH - This bit is set when the External Diode 3 channel meets or exceeds its programmed high limit. Bit 2 - E2HIGH - This bit is set when the External Diode 2 channel meets or exceeds its programmed high limit. Bit 1 - E1HIGH - This bit is set when the External Diode 1 channel meets or exceeds its programmed high limit. Bit 0 - IHIGH - This bit is set when the Internal Diode channel meets or exceeds its programmed high limit.
5.19
Low Limit Status Register
Table 5.24 Low Limit Status Register
ADDR. 36h
R/W R-C
REGISTER Low Limit Status
B7 E7 LOW
B6 E6 LOW
B5 E5 LOW
B4 E4 LOW
B3 E3 LOW
B2 E2 LOW
B1 E1 LOW
B0 ILOW
DEFAULT 00h
The Low Limit Status Register contains the status bits that are set when a temperature channel drops below the low limit for a number of consecutive readings as set by the consecutive alert counts (see Section 5.14). If any of these bits are set, then the LOW status bit in the Status Register is set. Reading from the Low Limit Status Register will clear all bits if the error condition has been removed. Reading from the register will also clear the LOW status bit in the Status Register. The ALERT pin will be set if any of these status bits are set. Bit 7 - E7LOW - This bit is set when the External Diode 7 channel drops below its programmed low limit. Bit 6 - E6LOW - This bit is set when the External Diode 6 channel drops below its programmed low limit. Bit 5- E5LOW - This bit is set when the External Diode 5 channel drops below its programmed low limit. Bit 4 - E4LOW - This bit is set when the External Diode 4 channel drops below its programmed low limit. Bit 3 - E3LOW - This bit is set when the External Diode 3 channel drops below its programmed low limit. Bit 2 - E2LOW - This bit is set when the External Diode 2 channel drops below its programmed low limit. Bit 1 - E1LOW - This bit is set when the External Diode 1 channel drops below its programmed low limit. Bit 0 - ILOW - This bit is set when the Internal Diode channel drops below its programmed low limit.
5.20
THERM Limit Status Register
Table 5.25 THERM Limit Status Register
ADDR 37h
R/W R-C
REGISTER THERM Limit Status
B7 E7 THERM
B6 E6 THERM
B5 E5 THERM
B4 E4 THERM
41
B3 E3 THERM
B2 E2 THERM
B1 E1 THERM
B0 I THERM
DEFAULT 00h
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1C Multiple Temperature Sensor with HW Thermal Shutdown & Hottest of Thermal Zones
Datasheet
The THERM Limit Status Register contains the status bits that are set when a temperature channel THERM Limit is exceeded for a number of consecutive readings as set by the consecutive therm counts (see Section 5.14). If any of these bits are set, then the THERM status bit in the Status Register is set. Reading from the THERM Limit Status Register will not clear the status bits. Once the temperature drops below the THERM Limit minus the THERM Hysteresis, the corresponding status bits will be automatically cleared. The THERM bit in the Status Register will be cleared when all individual channel THERM bits are cleared. Bit 7 - E7THERM - This bit is set when the External Diode 7 channel meets or exceeds it's programmed THERM Limit. Bit 6 - E6THERM - This bit is set when the External Diode 6 channel meets or exceeds it's programmed THERM Limit. Bit 5 - E5THERM - This bit is set when the External Diode 5 channel meets or exceeds it's programmed THERM Limit. Bit 4 - E4THERM - This bit is set when the External Diode 4 channel meets or exceeds it's programmed THERM Limit. Bit 3 - E3THERM - This bit is set when the External Diode 3 channel meets or exceeds it's programmed THERM Limit. Bit 2 - E2THERM - This bit is set when the External Diode 2 channel meets or exceeds it's programmed THERM Limit. Bit 1 - E1THERM - This bit is set when the External Diode 1 channel meets or exceeds it's programmed THERM limit. Bit 0- ITHERM - This bit is set when the Internal Diode channel meets or exceeds it's programmed THERM limit.
5.21
REC Configuration Register
Table 5.26 REC Configuration Register
ADDR 39h
R/W R/W
REGISTER REC Config
B7 E7 REC_n
B6 E6_ REC_n
B5 E5_ REC_n
B4 E4_ REC_n
B3 E3_ REC_n
B2 E2_ REC_n
B1 E1_ REC_n
B0 -
DEFAULT 00h
The REC Control Register controls the Resistance Error Correction circuitry for each of the external diode channels. Bits 7 -0- EX_REC_n - Disables the Resistance Error Correction (REC) for the External Diode X channel. `0' (default) - REC is enabled. `1' - REC is disabled.
5.22
Hottest Configuration Register
Table 5.27 Hottest Configuration Register
ADDR 3Ah
R/W R/W
REGISTER Hottest Config
B7 E7HOT
B6 E6HOT
B5 E5HOT
B4 E4HOT
B3 E3HOT
B2 E2HOT
B1 E1HOT
B0 IHOT
DEFAULT 00h
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The Hottest Configuration Register determines which External Diode Channels (if any) are compared during the "Hottest Of" comparison that is automatically performed at the end of every conversion cycle. Bits 7 - 0 - ExHOT - Controls whether the External Diode X temperature data is compared during the "Hottest Of" comparison. `0' (default) - The External Diode X channel is not compared during the "Hottest Of" Comparison. `1' - The External Diode X channel temperature data is compared to all other indicated channels during the "Hottest Of" Comparison. Bit 0 - IHOT - Controls whether the Internal Diode temperature data is compared during the "Hottest Of" comparison. `0' (default) - The Internal Diode channel is not compared during the "Hottest Of" Comparison. `1' - The Internal Diode channel temperature data is compared to all other indicated channels during the "Hottest Of" Comparison.
5.23
Channel Configuration Register
Table 5.28 Channel Configuration Register
ADDR 3Bh
R/W R/W
REGISTER Channel Config
B7 REM_H OT
B6 -
B5 -
B4 -
B3 EXT6_ APD
B2 EXT4_ APD
B1 EXT2_ APD
B0 -
DEFAULT 00h
The Channel Configuration Register determines which external diode channels are active in the device. Bit 7 - REM_HOT - Enables circuitry that will remember the last temperature channel that was determined to be the Hottest and flag an error if the hottest temperature channel changes. `0' (default) - The HOTTEST status bit will not be asserted if the hottest temperature channel changes. `1' - If the hottest temperature channel changes, then the HOTTEST status bit will be asserted. Bit 3 - EXT6_APD - Enables the DP6 / DN7 and DN6 / DP7 pins to support two anti-parallel diode connections versus a single diode connection. `0' (default) - The DP6 / DN7 and DN6 / DP7 pins do not support two anti-parallel diode connections. The pins will only monitor a single external diode (External Diode 6). `1' - The DP6 / DN7 and DN6 / DP7 pins support two anti-parallel diode connections (External Diode 6 and External Diode 7). Bit 2 - EXT4_APD - Enables the DP4 / DN5 and DN4 / DP5 pins to support two anti-parallel diode connections versus a single diode connection. `0' (default) - The DP4 / DN5 and DN4 / DP5 pins do not support two anti-parallel diode connections. The pins will only monitor a single external diode (External Diode 4). `1' - The DP4 / DN5 and DN4 / DP5 pins support two anti-parallel diode connections (External Diode 4 and External Diode 5). Bit 1 - EXT2_APD- Enables the DP2 / DN3 and DN2 / DP3 pins to support two anti-parallel diode connections versus a single diode connection. `0' (default) - The DP2 / DN3 and DN2 / DP3 pins do not support two anti-parallel diode connections. The pins will only monitor a single external diode (External Diode 2). `1' - The DP2 / DN3 and DN2 / DP3 pins support two anti-parallel diode connections (External Diode 2 and External Diode 3).
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5.24
Filter Control Register
Table 5.29 Filter Control Register
ADDR 40h
R/W R/W
REGISTER Filter Control
B7 AVG 7_EN
B6 AVG6 _EN
B5 AVG5 _EN
B4 AVG4 _EN
B3 AVG 3_EN
B2 AVG2 _EN
B1 AVG 1_EN
B0 -
DEFAULT 00h
The Filter Configuration Register controls the digital filter on the external diode channels. Bits 7 - 0 - AVGx_EN- Control the digital averaging that is applied to the External Diode X temperature measurements. `0' (default) - Digital Averaging is disabled. `1' - Digital averaging is enabled as a 4x running average for the External Diode X channel.
5.25
Product ID Register
Table 5.30 Product ID Register
ADDR FDh
R/W R
REGISTER Product ID
B7 0
B6 0
B5 1
B4 0
B3 1
B2 0
B1 0
B0 1
DEFAULT 29h EMC1428
The Product ID Register holds a unique value that identifies the device.
5.26
Manufacturer ID Register (FEh)
Table 5.31 Manufacturer ID Register
ADDR. FEh
R/W R
REGISTER Manufacturer ID
B7 0
B6 1
B5 0
B4 1
B3 1
B2 1
B1 0
B0 1
DEFAULT 5Dh
The Manufacturer ID Register holds an 8-bit word that identifies SMSC.
5.27
Revision Register (FFh)
Table 5.32 Revision Register
ADDR. FFh
R/W R
REGISTER Revision
B7 0
B6 0
B5 0
B4 0
B3 0
B2 0
B1 0
B0 1
DEFAULT 01h
The Revision register contains an 8 bit word that identifies the die revision.
Revision 0.62 (03-05-08)
44
SMSC EMC1428
DATASHEET
1C Multiple Temperature Sensor with HW Thermal Shutdown & Hottest of Thermal Zones
Datasheet
Chapter 6 Package Information
6.1
EMC1428 Package Drawing
Figure 6.1 16 pin QFN 4mm x 4mm Package Dimensions
SMSC EMC1428
45
Revision 0.62 (03-05-08)
DATASHEET
1C Multiple Temperature Sensor with HW Thermal Shutdown & Hottest of Thermal Zones
Datasheet
Figure 6.2 16 pin QFN 4mm x 4mm Package Drawing
Revision 0.62 (03-05-08)
46
SMSC EMC1428
DATASHEET
1C Multiple Temperature Sensor with HW Thermal Shutdown & Hottest of Thermal Zones
Datasheet
Figure 6.3 16 pin QFN 4mm x 4mm PCB Footprint
SMSC EMC1428
47
Revision 0.62 (03-05-08)
DATASHEET


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